(a) Field of the Invention
The invention relates to Integrated Circuit (IC) technology in general and more particularly relates to the use of semi-conductor devices to form voltage generators on an IC chip.
(b) Prior Art
The static non-volatile RAM chip and the newly developed dynamic non-volatile RAM chip are two types of semiconductor components which are used in conjunction with the processing of data. These components are usually used as memory elements. A typical static non-volatile RAM chip consists of a plurality of static non-volatile RAM cells. A typical non-volatile RAM cell consists of an EE PROM (Electrical Erasable Programmable Read Only Memory) cell connected to a latch. The latch is formed from a plurality (usually four) FETs connected in a cross-coupled configuration. Single FET control devices are connected to each half of the latch.
Usually, an on-chip voltage generator is provided for NVRAM. The generator produces a voltage which is needed for the operation of the non-volatile cell. Most of the non-volatile static RAM chips require only one high voltage level (e.g., above plus 5 volts) for programming or erasing. The classical electrical circuitry used to provide the high voltage level is a free-running oscillator and a charge pump. The charge pump is made to run in an open-ended manner or is clamped at a predetermined voltage. A more detailed discussion of prior art covering the non-volatile static RAM is given in an article entitled, "A 5 V-Only 16K EE PROM Utilizing Oxynitride Dielectrics and E PROM Redundancy," A. Gupta et al, p. 184 of the 1982 Digest of Technical Papers from the International Solid-State Circuit Conference. Another article entitled, "A Single 5 V Supply Non-Volatile Static RAM," Joseph Drori et al, p. 148 of the 1981 Digest of Technical Papers for the International Solid State Circuits Conference, gives an example of prior art non-volatile static RAM.
One of the drawbacks of the non-volatile static RAM is that it is a relatively low density device. The low density is due, in part, to the fact that a relatively large number of FET devices are used to form the cells of the non-volatile static RAM. A device which uses fewer FET devices will certainly yield a denser module.
The non-volatile dynamic RAM uses fewer FET devices and therefore provides a denser module. The newly developed non-volatile dynamic RAM cell consists of an EE PROM cell connected to a storage capacitor. One of the capacitor plates is attached to a fixed voltage and the other is coupled to an FET control device. The FET control device is also coupled to a sense amplifier. The sense amplifier senses the charge on the capacitor and when necessary initiates a refresh cycle for charging the cell.
Because of the density and other inherent characteristics, the non-volatile dynamic RAM utilizes a more complex voltage generating system than the non-volatile static RAM. The dynamic RAM voltage generating system must provide a plurality of different voltage levels. To this end, the rather simple voltage generating system which is used to drive the non-volatile static RAM cell cannot be used to drive the non-volatile dynamic RAM cell.